At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence Design Systems Inc. is looking for a motivated Lead Software Engineer: PCIe VIP R&D to work with us in Belo Horizonte, Brazil.As a Lead Software Engineer, you will be part of the VIPPCIE R&D team in the SVG group in Belo Horizonte, Brazil.The VIPPCIE R&D team works with PCIe verification IP. To understand more about what we do, you can visit PCIe VIP at Cadence.Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.Job Description:Responsible for software development and validation of PCIe Verification IP.Participate in development efforts of the PCIe product to meet customer use model, solution requirements, protocol specification, and execute necessary software development practices to create reusable and robust software solutions for verification of these interface protocols.Work with a multi-site and diverse team, effectively collaborating with a multi-location development team to contribute to PCIe verification IP development, milestones, technical roadmap, and people training for success.Work with technical support lead and key customers to resolve implementation or usage issues as Cadence VIP products are used within various verification environments, with timing critical to our customers' successes.Requirements:Bachelor's degree in Computer Science and 3+ years of experience or a related technical field with relevant 5+ years of experience.Extensive experience in modeling in C/C++ and a background in object-oriented programming, algorithms, and data structures.Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.Outstanding communication skills and ability to work collaboratively in a dynamic multi-location environment.Good communication skills in English and Portuguese.Nice to have:Working knowledge of PCI Express (PCIe) protocol or one or more protocols such as USB, NVME, SATA, Display Port, etc.Knowledge of Verilog/System Verilog languages and OVM/UVM verification methodologies.Experience with digital logic design or IP/SoC level verification flow.Customer orientation and knowledge of the EDA tool flow.Additional Job Details:Employment category: CLTEmployment term: 40 hours/week.Competitive benefits.Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil.About Cadence Design Systems:Cadence is the only company that provides the expertise, tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial, and other market segments. For more information, access http://www.cadence.com.We’re doing work that matters. Help us solve what others can’t.
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