Lead Software Engineer: PCle VIP R&DLead Software Engineer: PCle VIP R&DApply locations BELO HORIZONTE time type Full time posted on Posted 4 Days Ago job requisition id R49445At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence Design Systems Inc. is looking for a motivated Lead Software Engineer: PCle VIP R&D to work with us in Belo Horizonte, Brazil.As a Lead Software Engineer, you will be part of the VIPPCIE R&D team in the SVG group in Belo Horizonte, Brazil.The VIPPCIE R&D team works with PCIe verification IP. To understand more on what we do, you can visit PCIe VIP at Cadence.Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.Job Description:Candidate will be responsible for software development and validation of PCIe Verification IP.As a Lead Software Engineer, candidate is expected to participate in development efforts of the PCIe product to meet customer use model, solution requirements, protocol specification and execute necessary SW development practices to create reusable robust software solution to enable verification of these interface protocols.Candidate should be able to work with multi-site and diverse team. You need to effectively collaborate with a multi-location development team to contribute in PCIe verification IP development, milestones technical roadmap and people training for success.The candidate is also expected to work with technical support lead and key customers to resolve implementation or usage issues as Cadence VIP products are used within various verification environments and timing critical to our customer’s successes.Requirements:Complete Bachelors degree in Computer Science and 3+ years of experience or a related technical field with relevant 5+ years of experience.Extensive experience in modeling in C/C++ and background in object-oriented, algorithms, and data structures.Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment.Good communication in English and Portuguese.Nice to have:Working knowledge of PCI Express (PCIe) protocol or one or more protocols USB, NVME, SATA, Display Port, etc.Knowledge of Verilog/System Verilog languages and OVM/UVM verification methodologies.Experience with digital logic design or IP/SoC level Verification flow.Customer orientation and knowledge of the EDA tool flow.Additional Job Details:Employment category: CLTEmployment term: 40 hours/week.Competitive benefits.Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.About Cadence Design Systems:Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.We’re doing work that matters. Help us solve what others can’t.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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